编辑推荐
国内多所院校采用；反映了纳米级别CMOS技术的广泛应用和技术的发展。
作者简介
S.M.Kang韩国科学技术院（KAIST）的院长，并任电气工程教授。他曾是美国伊利诺伊大学香槟分校电气和计算机工程系的系主任和教授，美国加州大学圣塔克鲁兹分校工程系主任，以及美国加州大学默塞德分校的名誉校长。Y.Leblebici电气工程教授，并在位于洛桑的瑞士联邦理工学院担任微电子系统实验室主任。他曾在土耳其萨班哲大学任微电子项目协调人，也曾是是美国伍斯特理工学院电气和计算机工程副教授以及土耳其伊斯坦布尔科技大学电气工程副教授。C.Kim韩国高丽大学电气和电子工程教授。他曾是美国加州大学洛杉矶分校和加州大学圣特鲁兹大学的客座教授，也曾在得克萨斯州奥斯汀的IBM微电子部门工作，参与单元处理器设计。
目录
CONTENTS
目录
Chapter 1Introduction
概论1
1.1 Historical Perspective
发展历史1
1.2 Objective and Organization of the Book
本书的目标和结构5
1.3 A Circuit Design Example
电路设计举例8
1.4 Overview of VLSI Design Methodologies
VLSI 设计方法综述18
1.5 VLSI Design Flow
VLSI 设计流程20
1.6 Design Hierarchy
设计分层23
1.7 Concepts of Regularity, Modularity, and Locality
规范化、模块化和本地化的概念26
1.8 VLSI Design Styles
VLSI 的设计风格28
1.9 Design Quality
设计质量39
1.10 Packaging Technology
封装技术41
1.11 Computer-Aided Design Technology
计算机辅助设计技术44
Exercise Problems
习题46
Chapter 2Fabrication of MOSFETs
MOS 场效应管的制造49
2.1 Introduction
概述49
2.2 Fabrication Process Flow: Basic Steps
制造工艺的基本步骤50
2.3 The CMOS n-Well Process
CMOS n 阱工艺60
2.4 Evolution of CMOS Technology
CMOS 技术的发展67
2.5 Layout Design Rules
版图设计规则74
2.6 Full-Custom Mask Layout Design
全定制掩膜版图设计78
Exercise Problems
习题82
Chapter 3MOS Transistor
MOS 晶体管92
3.1 The Metal Oxide Semiconductor (MOS) Structure
金属-氧化物-半导体 (MOS) 结构92
3.2 The MOS System Under External Bias
外部偏置下的 MOS 系统96
3.3 Structure and Operation of the MOS Transistor (MOSFET)
MOS 场效应管 (MOSFET) 的结构和作用99
3.4 MOSFET Current-Voltage Characteristics
MOSFET 的电流-电压特性109
3.5 MOSFET Scaling and Small-Geometry Effects
MOSFET 的收缩和小尺寸效应120
3.6 MOSFET Capacitances
MOSFET 电容151
Exercise Problems
习题162
Chapter 4Modeling of MOS Transistors Using SPICE
用 SPICE 进行 MOS 管建模167
4.1 Introduction
概述167
4.2 Basic Concepts
基本概念168
4.3 The Level 1 Model Equations
一级模型方程170
4.4 The Level 2 Model Equations
二级模型方程174
4.5 The Level 3 Model Equations
三级模型方程178
4.6 State-of-the-Art MOSFET Models
先进的 MOSFET 模型179
4.7 Capacitance Models
电容模型180
4.8 Comparison of the SPICE MOSFET Models
SPICE MOSFET 模型的比较184
Appendix: Typical SPICE Model Parameters
附录典型 SPICE 模型参数186
Exercise Problems
习题192
Chapter 5MOS Inverters: Static Characteristics
MOS 反相器的静态特性194
5.1 Introduction
概述194
5.2 Resistive-Load Inverter
电阻负载型反相器202
5.3 Inverters with MOSFET Load
MOSFET 负载反相器211
5.4 CMOS Inverter
CMOS 反相器221
Appendix: Sizing Trends of CMOS Inverter with Small-Geometry Devices
附录小几何尺寸器件中 CMOS 反相器尺寸的发展趋势239
Exercise Problems
习题241
Chapter 6MOS Inverters: Switching Characteristics and Interconnect Effects
MOS 反相器的开关特性和体效应245
6 1Introduction
概述245
6 2Delay-Time Denitions
延迟时间的定义247
6.3 Calculation of Delay Times
延迟时间的计算249
6.4 Inverter Design with Delay Constraints
延迟限制下的反相器设计257
6.5 Estimation of Interconnect Parasitics
互连线电容的估算267
6.6 Calculation of Interconnect Delay
互连线延迟的计算280
6.7 Switching Power Dissipation of CMOS Inverters
CMOS 反相器的开关功耗288
Appendix: Super Buffer Design
附录超级缓冲器的设计297
Exercise Problems
习题300
Chapter 7Combinational MOS Logic Circuits
组合 MOS 逻辑电路305
7.1 Introduction
概述305
7.2 MOS Logic Circuits with Pseudo-nMOS (pMOS) Loads
带伪 nMOS(pMOS) 负载的 MOS 逻辑电路306
7.3 CMOS Logic Circuits
CMOS 逻辑电路319
7.4 Complex Logic Circuits
复杂逻辑电路326
7.5 CMOS Transmission Gates (Pass Gates)
CMOS 传输门339
Exercise Problems
习题349
Chapter 8Sequential MOS Logic Circuits
时序 MOS 逻辑电路356
8.1 Introduction
概述356
8.2 Behavior of Bistable Elements
双稳态元件的特性357
8.3 The SR Latch Circuit
SR 锁存电路363
8.4 Clocked Latch and Flip-Flop Circuits
钟控锁存器和触发器电路368
8.5 Timing-Related Parameters of Clocked Storage Elements
时钟存储器件的相关时序特性376
8.6 CMOS D-Latch and Edge-Triggered Flip-Flop
CMOS 的 D 锁存器和边沿触发器378
8.7 Pulsed Latch-Based Clocked Storage Elements
以时钟存储元件为基础的脉冲锁存器384
8 8Sense-Amplier-Based Flip-Flops
基于灵敏放大器的触发器电路386
8.9 Logic Embedding in Clocked Storage Elements
时钟存储器件中的逻辑嵌入388
8.10 Power Consumption of Clocking System and Power Savings Methodologies
时钟系统的能耗及其节能措施389
Appendix
附录391
Exercise Problems
习题394
Chapter 9Dynamic Logic Circuits
动态逻辑电路398
9.1 Introduction
概述398
9.2 Basic Principles of Pass Transistor Circuits
传输晶体管电路的基本原理
9.3 Voltage Bootstrapping
电压自举技术412
9.4 Synchronous Dynamic Circuit Techniques
同步动态电路技术416
9.5 Dynamic CMOS Circuit Techniques
动态 CMOS 电路技术421
9.6 High-Performance Dynamic CMOS Circuits
高性能动态逻辑 CMOS 电路425
Exercise Problems
习题442
Chapter 10Semiconductor Memories
半导体存储器447
10.1 Introduction
概述447
10.2 Dynamic Random Access Memory (DRAM)
动态随机存储器 (DRAM)452
10.3 Static Random Access Memory (SRAM)
静态随机存储器 (SRAM)481
10.4 Nonvolatile Memory
非易失存储器497
10.5 Flash Memory
闪存510
10.6 Ferroelectric Random Access Memory (FRAM)
铁电随机存储器 (FRAM)518
Exercise Problems
习题521
Chapter 11Low-Power CMOS Logic Circuits
低功耗 CMOS 逻辑电路527
11.1 Introduction
概述527
11.2 Overview of Power Consumption
功耗综述528
11.3 Low-Power Design Through Voltage Scaling
电压按比例降低的低功率设计541
11.4 Estimation and Optimization of Switching Activity
开关激活率的估算和优化552
11.5 Reduction of Switched Capacitance
减小开关电容558
11.6 Adiabatic Logic Circuits
绝热逻辑电路560
Exercise Problems
习题568
Chapter 12Arithmetic Building Blocks
算术组合模块569
12.1 Introduction
概述569
12.2 Adder
加法器569
12.3 Multipliers
乘法器580
12.4 Shifter
移位器586
Exercise Problems
习题588
Chapter 13Clock and I/O Circuits
时钟电路与输入输出电路592
13.1 Introduction
概述592
13.2 ESD Protection
静电放电 (ESD) 保护592
13.3 Input Circuits
输入电路596
13.4 Output Circuits and L(di/dt) Noise
输出电路和 L(di/dt) 噪声600
13.5 On-Chip Clock Generation and Distribution
片内时钟生成和分配605
13.6 Latch-Up and Its Prevention
闩锁现象及其预防措施620
Appendix: Network-on-Chip: An Emerging Paradigm for Next-Generation SoCs
附录芯片网络：下一代片上系统的新范例627
Exercise Problems
习题631
Chapter 14Design for Manufacturability
产品化设计633
14.1 Introduction
概述633
14.2 Process Variations
工艺变化634
14 3Basic Concepts and Denitions
基本概念和定义636
14.4 Design of Experiments and Performance Modeling
实验设计与性能建模642
14.5 Parametric Yield Estimation
参数成品率的估计650
14.6 Parametric Yield Maximization
参数成品率的最大值655
14.7 Worst-Case Analysis
最坏情况分析657
14.8 Performance Variability Minimization
性能参数变化的最小化663
Exercise Problems
习题666
Chapter 15Design for Testability
可测试性设计670
15.1 Introduction
概述670
15.2 Fault Types and Models
故障类型和模型670
15.3 Controllability and Observability
可控性和可观察性674
15.4 Ad Hoc Testable Design Techniques
专用可测试性设计技术675
15.5 Scan-Based Techniques
基于扫描的技术678
15.6 Built-In Self-Test (BIST) Techniques
内建自测 (BIST) 技术680
15.7 Current Monitoring IDDQ Test
电流监控 IDDQ 检测683
Exercise Problems
习题684
References
参考文献685
Index
索引691
序言
ABOUT THE AUTHORS
Sung-Mo “Steve” Kang received his PhD in electrical engineering from the University of California, Berkeley. He has worked on the development of full- custom CMOS VLSI chips, including the world’s rst 32-bit full CMOS micro- processor and peripheral chips at AT＆T Bell Laboratories in Murray Hill, New Jersey. He has taught digital integrated circuits at the University of Illinois at Urbana-Champaign； the University of California, Santa Cruz； the University of California, Merced； and the Korea Advanced Institute of Science and Technology (KAIST) in Daejeon, Korea. He has also given invited lectures and tutorials on CMOS digital circuits, reliability, and computer-aided design of VLSI circuits and systems at major conferences and universities globally.
Dr. Kang is a fellow of IEEE, ACM, and AAAS and has received many awards, including the IEEE Millennium Medal, IEEE Graduate Teaching Technical Field Award, IEEE CAS Society M. E. Van Valkenburg Award, IEEE CAS Society Tech- nical Excellence Award, SRC Technical Excellence Award, and Chang-Lin Tien Education Leadership Award. He has served as Department Head of the University of Illinois at Urbana-Champaign； Dean of Engineering at the University of California, Santa Cruz； Chancellor of the University of California, Merced； and President of KAIST, Daejeon, Korea.
Yusuf Leblebici received a PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He has been a visiting assistant profes- sor of electrical and computer engineering at the University of Illinois at Urbana- Champaign, associate professor of electrical and electronics engineering at Istanbul Technical University, and associate professor of electrical and computer engineering at Worcester Polytechnic Institute. He also served as the microelectronics program coordinator at Sabanci University. Currently, he is a full (chair) professor at the Swiss Federal Institute of Technology in Lausanne, Switzerland, and director of the Microelectronic Systems Laboratory. His research interests include design of high- performance CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis. He is a fellow of IEEE and re- cipient of the NATO Science Fellowship Award, the Young Scientist Award of the Turkish Scientic and Technological Research Council, and the Joseph Samuel Satin Distinguished Fellow Award of the Worcester Polytechnic Institute. He was elected as Distinguished Lecturer of the IEEE Circuits and Systems Society for 2010–2011.
Chulwoo Kim received BS and MS degrees inelectronicsengineeringfrom Korea University, and a PhD in electrical and computer engineering from the Uni- versity of Illinois at Urbana-Champaign. In 1999, he worked as a summer intern at Design Technology at Intel Corporation, Santa Clara, California. In May 2001, he joined IBM Microelectronics Division in Austin, Texas, where he was involved in cell processor design. Since September 2002, he has been with the Department of Elec- tronics and Computer Engineering at Korea University, where he is currently a pro- fessor. He was a visiting professor at the University of California, Los Angeles and at the University of California, Santa Cruz. His current research interests are in the areas of wireline transceiver, memory, power management, and data converters.
Dr. Kim received the Samsung HumanTech Thesis Contest Bronze Award, the ISLPED Low-Power Design Contest Award, the DAC Student Design Contest Award, the SRC Inventor Recognition Award, the Young Scientist Award from the Ministry of Science and Technology of Korea, the Seoktop Award for excellence in teaching, and the ASP-DAC Best Design Award. He is currently on the editorial board of IEEE Transactions on VLSI Systems and on the Technical Program Com- mittee of the IEEE International Solid-State Circuits Conference.
作 者 简 介
Sung-Mo (Steve) Kang（康松默） 于美国加州大学伯克利分校电机工程系取得博士 学位，主要研究全定制 CMOS VLSI 芯片的
国内多所院校采用；反映了纳米级别CMOS技术的广泛应用和技术的发展。
作者简介
S.M.Kang韩国科学技术院（KAIST）的院长，并任电气工程教授。他曾是美国伊利诺伊大学香槟分校电气和计算机工程系的系主任和教授，美国加州大学圣塔克鲁兹分校工程系主任，以及美国加州大学默塞德分校的名誉校长。Y.Leblebici电气工程教授，并在位于洛桑的瑞士联邦理工学院担任微电子系统实验室主任。他曾在土耳其萨班哲大学任微电子项目协调人，也曾是是美国伍斯特理工学院电气和计算机工程副教授以及土耳其伊斯坦布尔科技大学电气工程副教授。C.Kim韩国高丽大学电气和电子工程教授。他曾是美国加州大学洛杉矶分校和加州大学圣特鲁兹大学的客座教授，也曾在得克萨斯州奥斯汀的IBM微电子部门工作，参与单元处理器设计。
目录
CONTENTS
目录
Chapter 1Introduction
概论1
1.1 Historical Perspective
发展历史1
1.2 Objective and Organization of the Book
本书的目标和结构5
1.3 A Circuit Design Example
电路设计举例8
1.4 Overview of VLSI Design Methodologies
VLSI 设计方法综述18
1.5 VLSI Design Flow
VLSI 设计流程20
1.6 Design Hierarchy
设计分层23
1.7 Concepts of Regularity, Modularity, and Locality
规范化、模块化和本地化的概念26
1.8 VLSI Design Styles
VLSI 的设计风格28
1.9 Design Quality
设计质量39
1.10 Packaging Technology
封装技术41
1.11 Computer-Aided Design Technology
计算机辅助设计技术44
Exercise Problems
习题46
Chapter 2Fabrication of MOSFETs
MOS 场效应管的制造49
2.1 Introduction
概述49
2.2 Fabrication Process Flow: Basic Steps
制造工艺的基本步骤50
2.3 The CMOS n-Well Process
CMOS n 阱工艺60
2.4 Evolution of CMOS Technology
CMOS 技术的发展67
2.5 Layout Design Rules
版图设计规则74
2.6 Full-Custom Mask Layout Design
全定制掩膜版图设计78
Exercise Problems
习题82
Chapter 3MOS Transistor
MOS 晶体管92
3.1 The Metal Oxide Semiconductor (MOS) Structure
金属-氧化物-半导体 (MOS) 结构92
3.2 The MOS System Under External Bias
外部偏置下的 MOS 系统96
3.3 Structure and Operation of the MOS Transistor (MOSFET)
MOS 场效应管 (MOSFET) 的结构和作用99
3.4 MOSFET Current-Voltage Characteristics
MOSFET 的电流-电压特性109
3.5 MOSFET Scaling and Small-Geometry Effects
MOSFET 的收缩和小尺寸效应120
3.6 MOSFET Capacitances
MOSFET 电容151
Exercise Problems
习题162
Chapter 4Modeling of MOS Transistors Using SPICE
用 SPICE 进行 MOS 管建模167
4.1 Introduction
概述167
4.2 Basic Concepts
基本概念168
4.3 The Level 1 Model Equations
一级模型方程170
4.4 The Level 2 Model Equations
二级模型方程174
4.5 The Level 3 Model Equations
三级模型方程178
4.6 State-of-the-Art MOSFET Models
先进的 MOSFET 模型179
4.7 Capacitance Models
电容模型180
4.8 Comparison of the SPICE MOSFET Models
SPICE MOSFET 模型的比较184
Appendix: Typical SPICE Model Parameters
附录典型 SPICE 模型参数186
Exercise Problems
习题192
Chapter 5MOS Inverters: Static Characteristics
MOS 反相器的静态特性194
5.1 Introduction
概述194
5.2 Resistive-Load Inverter
电阻负载型反相器202
5.3 Inverters with MOSFET Load
MOSFET 负载反相器211
5.4 CMOS Inverter
CMOS 反相器221
Appendix: Sizing Trends of CMOS Inverter with Small-Geometry Devices
附录小几何尺寸器件中 CMOS 反相器尺寸的发展趋势239
Exercise Problems
习题241
Chapter 6MOS Inverters: Switching Characteristics and Interconnect Effects
MOS 反相器的开关特性和体效应245
6 1Introduction
概述245
6 2Delay-Time Denitions
延迟时间的定义247
6.3 Calculation of Delay Times
延迟时间的计算249
6.4 Inverter Design with Delay Constraints
延迟限制下的反相器设计257
6.5 Estimation of Interconnect Parasitics
互连线电容的估算267
6.6 Calculation of Interconnect Delay
互连线延迟的计算280
6.7 Switching Power Dissipation of CMOS Inverters
CMOS 反相器的开关功耗288
Appendix: Super Buffer Design
附录超级缓冲器的设计297
Exercise Problems
习题300
Chapter 7Combinational MOS Logic Circuits
组合 MOS 逻辑电路305
7.1 Introduction
概述305
7.2 MOS Logic Circuits with Pseudo-nMOS (pMOS) Loads
带伪 nMOS(pMOS) 负载的 MOS 逻辑电路306
7.3 CMOS Logic Circuits
CMOS 逻辑电路319
7.4 Complex Logic Circuits
复杂逻辑电路326
7.5 CMOS Transmission Gates (Pass Gates)
CMOS 传输门339
Exercise Problems
习题349
Chapter 8Sequential MOS Logic Circuits
时序 MOS 逻辑电路356
8.1 Introduction
概述356
8.2 Behavior of Bistable Elements
双稳态元件的特性357
8.3 The SR Latch Circuit
SR 锁存电路363
8.4 Clocked Latch and Flip-Flop Circuits
钟控锁存器和触发器电路368
8.5 Timing-Related Parameters of Clocked Storage Elements
时钟存储器件的相关时序特性376
8.6 CMOS D-Latch and Edge-Triggered Flip-Flop
CMOS 的 D 锁存器和边沿触发器378
8.7 Pulsed Latch-Based Clocked Storage Elements
以时钟存储元件为基础的脉冲锁存器384
8 8Sense-Amplier-Based Flip-Flops
基于灵敏放大器的触发器电路386
8.9 Logic Embedding in Clocked Storage Elements
时钟存储器件中的逻辑嵌入388
8.10 Power Consumption of Clocking System and Power Savings Methodologies
时钟系统的能耗及其节能措施389
Appendix
附录391
Exercise Problems
习题394
Chapter 9Dynamic Logic Circuits
动态逻辑电路398
9.1 Introduction
概述398
9.2 Basic Principles of Pass Transistor Circuits
传输晶体管电路的基本原理
9.3 Voltage Bootstrapping
电压自举技术412
9.4 Synchronous Dynamic Circuit Techniques
同步动态电路技术416
9.5 Dynamic CMOS Circuit Techniques
动态 CMOS 电路技术421
9.6 High-Performance Dynamic CMOS Circuits
高性能动态逻辑 CMOS 电路425
Exercise Problems
习题442
Chapter 10Semiconductor Memories
半导体存储器447
10.1 Introduction
概述447
10.2 Dynamic Random Access Memory (DRAM)
动态随机存储器 (DRAM)452
10.3 Static Random Access Memory (SRAM)
静态随机存储器 (SRAM)481
10.4 Nonvolatile Memory
非易失存储器497
10.5 Flash Memory
闪存510
10.6 Ferroelectric Random Access Memory (FRAM)
铁电随机存储器 (FRAM)518
Exercise Problems
习题521
Chapter 11Low-Power CMOS Logic Circuits
低功耗 CMOS 逻辑电路527
11.1 Introduction
概述527
11.2 Overview of Power Consumption
功耗综述528
11.3 Low-Power Design Through Voltage Scaling
电压按比例降低的低功率设计541
11.4 Estimation and Optimization of Switching Activity
开关激活率的估算和优化552
11.5 Reduction of Switched Capacitance
减小开关电容558
11.6 Adiabatic Logic Circuits
绝热逻辑电路560
Exercise Problems
习题568
Chapter 12Arithmetic Building Blocks
算术组合模块569
12.1 Introduction
概述569
12.2 Adder
加法器569
12.3 Multipliers
乘法器580
12.4 Shifter
移位器586
Exercise Problems
习题588
Chapter 13Clock and I/O Circuits
时钟电路与输入输出电路592
13.1 Introduction
概述592
13.2 ESD Protection
静电放电 (ESD) 保护592
13.3 Input Circuits
输入电路596
13.4 Output Circuits and L(di/dt) Noise
输出电路和 L(di/dt) 噪声600
13.5 On-Chip Clock Generation and Distribution
片内时钟生成和分配605
13.6 Latch-Up and Its Prevention
闩锁现象及其预防措施620
Appendix: Network-on-Chip: An Emerging Paradigm for Next-Generation SoCs
附录芯片网络：下一代片上系统的新范例627
Exercise Problems
习题631
Chapter 14Design for Manufacturability
产品化设计633
14.1 Introduction
概述633
14.2 Process Variations
工艺变化634
14 3Basic Concepts and Denitions
基本概念和定义636
14.4 Design of Experiments and Performance Modeling
实验设计与性能建模642
14.5 Parametric Yield Estimation
参数成品率的估计650
14.6 Parametric Yield Maximization
参数成品率的最大值655
14.7 Worst-Case Analysis
最坏情况分析657
14.8 Performance Variability Minimization
性能参数变化的最小化663
Exercise Problems
习题666
Chapter 15Design for Testability
可测试性设计670
15.1 Introduction
概述670
15.2 Fault Types and Models
故障类型和模型670
15.3 Controllability and Observability
可控性和可观察性674
15.4 Ad Hoc Testable Design Techniques
专用可测试性设计技术675
15.5 Scan-Based Techniques
基于扫描的技术678
15.6 Built-In Self-Test (BIST) Techniques
内建自测 (BIST) 技术680
15.7 Current Monitoring IDDQ Test
电流监控 IDDQ 检测683
Exercise Problems
习题684
References
参考文献685
Index
索引691
序言
ABOUT THE AUTHORS
Sung-Mo “Steve” Kang received his PhD in electrical engineering from the University of California, Berkeley. He has worked on the development of full- custom CMOS VLSI chips, including the world’s rst 32-bit full CMOS micro- processor and peripheral chips at AT＆T Bell Laboratories in Murray Hill, New Jersey. He has taught digital integrated circuits at the University of Illinois at Urbana-Champaign； the University of California, Santa Cruz； the University of California, Merced； and the Korea Advanced Institute of Science and Technology (KAIST) in Daejeon, Korea. He has also given invited lectures and tutorials on CMOS digital circuits, reliability, and computer-aided design of VLSI circuits and systems at major conferences and universities globally.
Dr. Kang is a fellow of IEEE, ACM, and AAAS and has received many awards, including the IEEE Millennium Medal, IEEE Graduate Teaching Technical Field Award, IEEE CAS Society M. E. Van Valkenburg Award, IEEE CAS Society Tech- nical Excellence Award, SRC Technical Excellence Award, and Chang-Lin Tien Education Leadership Award. He has served as Department Head of the University of Illinois at Urbana-Champaign； Dean of Engineering at the University of California, Santa Cruz； Chancellor of the University of California, Merced； and President of KAIST, Daejeon, Korea.
Yusuf Leblebici received a PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He has been a visiting assistant profes- sor of electrical and computer engineering at the University of Illinois at Urbana- Champaign, associate professor of electrical and electronics engineering at Istanbul Technical University, and associate professor of electrical and computer engineering at Worcester Polytechnic Institute. He also served as the microelectronics program coordinator at Sabanci University. Currently, he is a full (chair) professor at the Swiss Federal Institute of Technology in Lausanne, Switzerland, and director of the Microelectronic Systems Laboratory. His research interests include design of high- performance CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis. He is a fellow of IEEE and re- cipient of the NATO Science Fellowship Award, the Young Scientist Award of the Turkish Scientic and Technological Research Council, and the Joseph Samuel Satin Distinguished Fellow Award of the Worcester Polytechnic Institute. He was elected as Distinguished Lecturer of the IEEE Circuits and Systems Society for 2010–2011.
Chulwoo Kim received BS and MS degrees inelectronicsengineeringfrom Korea University, and a PhD in electrical and computer engineering from the Uni- versity of Illinois at Urbana-Champaign. In 1999, he worked as a summer intern at Design Technology at Intel Corporation, Santa Clara, California. In May 2001, he joined IBM Microelectronics Division in Austin, Texas, where he was involved in cell processor design. Since September 2002, he has been with the Department of Elec- tronics and Computer Engineering at Korea University, where he is currently a pro- fessor. He was a visiting professor at the University of California, Los Angeles and at the University of California, Santa Cruz. His current research interests are in the areas of wireline transceiver, memory, power management, and data converters.
Dr. Kim received the Samsung HumanTech Thesis Contest Bronze Award, the ISLPED Low-Power Design Contest Award, the DAC Student Design Contest Award, the SRC Inventor Recognition Award, the Young Scientist Award from the Ministry of Science and Technology of Korea, the Seoktop Award for excellence in teaching, and the ASP-DAC Best Design Award. He is currently on the editorial board of IEEE Transactions on VLSI Systems and on the Technical Program Com- mittee of the IEEE International Solid-State Circuits Conference.
作 者 简 介
Sung-Mo (Steve) Kang（康松默） 于美国加州大学伯克利分校电机工程系取得博士 学位，主要研究全定制 CMOS VLSI 芯片的
| ISBN | 9787121248047 |
|---|---|
| 出版社 | 电子工业出版社 |
| 作者 | Sung-Mo Kang等 |
| 尺寸 | 16 |